This invention relates to the field of integrated circuits. More particularly the invention relates to voltage tolerant high speed input circuits.
The input circuits of an integrated circuit are particularly susceptible to overvoltage conditions, because they are directly connected to devices that are external to the integrated circuit. Therefore, they may receive voltage spikes both during normal operation of the system of which they are a part, and when abnormal conditions are present. For example, when components within the system are powered up or powered down, voltage spikes may be generated along the buss that ties the various components together. The input buffers need to be resilient to these voltage spikes, in order to protect the rest of the circuits of the integrated circuit in which they reside.
Various input buffer designs have been developed to protect an integrated circuit from the damage that is created by overvoltage. However, these designs tend to impede the desired operation of the input circuit as a whole, in that the buffer tends to not propagate a signal with the speed that is required by modern electrical systems.
What is needed, therefore, is an input buffer design that protects an integrated circuit from overvoltage conditions, and does so without unduly compromising the speed of the input buffer.
The above and other needs are met by an improvement in a high speed input buffer of the type having a first connection in electrical communication with a positive voltage source and a second connection in electrical communication with a negative voltage source. A first native transistor is functionally disposed between the positive voltage source and the first connection. A first contact of the first native transistor is electrically connected to the positive voltage source and a second contact of the first native transistor is electrically connected to the first connection. A second native transistor is functionally disposed between the negative voltage source and the second connection. A first contact of the second native transistor is electrically connected to the negative voltage source and a second contact of the second native transistor is electrically connected to the second connection.
Thus, the input buffer of the present invention avoids various problems associated with prior art devices by utilizing native pass gate transistors between the buffer circuit and the high and low voltage input pads. Using native pass gate transistors in this manner advantageously limits the voltage exposure of the input buffer to a value that is relatively close to, but preferably no more than the value of the supply voltage. The threshold voltage and the back bias coefficient of threshold voltage of the native pass gate transistors are preferably very low, such that the transistors are able to pass voltages all the way to the supply voltage.
In various preferred embodiments, one or both of the first native transistor and the second native transistor are native NMOS transistors. The high speed input buffer alternately includes at least one leakage element having a first electrical connection and a second electrical connection. The first electrical connection of the leakage element is electrically connected to the second contact of the first native transistor and the second electrical connection of the leakage element is electrically connected to a VSS line. Alternately or additionally, the first electrical connection of the leakage element is electrically connected to the second contact of the second native transistor and the second electrical connection of the leakage element is electrically connected to a VSS line. The leakage element or elements may be one or more of either a resistor or an NMOS transistor, where a gate contact of the NMOS transistor is also electrically connected the second contact of either the first or second native transistor with which it is associated.